Time-area efficient multiplier-free filter architectures for FPGA implementation
نویسندگان
چکیده
Simultaneous design of multiplier-free filters and their hardware imp1 ementation in Xilinx Field Programmable Gate Array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low oirder sections. The complexity of the design algorithm is O(fi1ter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Timearea efficiency and performance of the architectures are considerably above any known approach.
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